Weak current College】 【using PLL design-time problems --- Power By】 【China power house network.

<br> In order to meet ASIC design time schedule requirements, many engineers are phase-locked loop (PLL). PLL with some desirable features, including the clock multiplier capacity, clock duty cycle of correction capabilities, and clock distribution delay the Elimination of .capacity. These characteristics allow designers to use cheap low frequency crystals as its tablets, external clock source and the ensuing chip multiplier to generate any number of high-frequency internal clock signal. They also enable designers to keep the build-time window and chip clock .source edge alignment methods to control those Windows and chip interface clock-output delay. <br> Although the structure and function looks simple, but full of various PLL hidden complexity, the complexity is likely to even the best designers. Today's ASIC technology in PLL .design is becoming more and more difficult, because the kernel thin oxide devices on the left of the threshold of power supply voltage peak reserves is more limited. These devices are often required to satisfy the objective of working frequency and maintain the flexibility of the supply voltage .. However, the power supply voltage peak reserves reduce the PLL of adverse impact noise characteristics. <br> Structure and operation <br> To truly understood PLL internal performance issues, we must first understand its structure and working principle. PLL's advanced structure seems to .be intuitive and straightforward, it consists of a phase detector, charge pumps, loop filter and voltage controlled oscillator (VCO). PLL circuit is started immediately after entering an "unlock" State because the VCO output frequency of the benchmarks and split frequency-independent .. <br> However, the negative feedback loop by bringing together a cyclical reference input and output of the VCO segmentation clock rise between phase error to adjust the VCO output frequency. Integrated VCO phase error makes output frequency close to the base segmentation. When you .reach the "locked" PLL, phase detector detected phase error close to zero, this is because the VCO output frequency and phase partitioning and base frequency and phase. Because phase detector output only and VCO segmentation, therefore PLL output frequency than baseline and feedback input .frequency high N times, which makes the PLL to complete the multiplier. <br> In addition, if the clock distribution is added to the feedback pathway, the PLL clock signal will be allocated at the reference signals, to delay the effective elimination clock distribution .. <br> PLL internal function block may be represented by a variable number of analog and digital circuit, digital circuit even in extreme situations. However, whether the digital circuit or analog circuits, PLL completed the phase of the clock signal generation and calibration of .analog functions. And simulation function block, they are also faced with noise such as today's mixed-signal ASIC harsh environments common and unavoidable simulation technology challenges. If PLL cannot make good noise response, it will cause the output clock from its ideal values of time .transform offset. <br> Output clock phase of these time transform offset is often called jitter (jitter). Jitter will build time by throwing an upset against the internal timing paths have disastrous effects, also by throwing an led the establishment of a data transfer .error-hold time disrupting effect tablet external interface instead. At the same time, other performance issues (such as instability, lack of adequate frequency range, locking problems and static phase offset) also affects the PLL design. Output jitter is one of the most .important issue, and is also the most rare PLL design to fit one of the topics addressed. <br> By on-chip and chip-signal source to generate power and substrate noise with high data dependence, and may have a large number of including .low frequency, frequency component. Substrate noise often does not like power noise that have a large number of low-frequency components, because in the basement and no obvious between the power supply DC decline. In the worst conditions, PLL occur power noise level and .noise level basement respectively nominal supply voltage of 10% and 5%. <br> The actual basal noise level depends on the IC manufacturing process used by the nature of the floor. In order to reduce the risk of a latch, many IC production technology .used in similar heavily doped base of light-doped extension. These substrates will tend to be long distance on the chip substrate noise transmission, making noise not readily available in through protection ring and additional base tap is being eliminated. <br> Power and substrate .noise VCO output caused by the shift (which causes the accumulation of multiple cycles, until the settlement of noise pulse phase) which have an impact on the PLL, without affecting the PLL to the loop bandwidth of the qualified rate on frequency calibration error. As .a result of phase error can accumulate more than one cycle, so the worst case of output jitter is usually a square wave by low-frequency noise. If PLL underdamped, close to the loop bandwidth of noise even obvious. In addition, the PLL is .also close to the loop bandwidth frequency input jitter on zoom in benchmarks, especially when it owes to the damping. <br> Output jitter types <br> Output jitter can use several methods to measure-relative to the absolute time and relative to other signals .or relative to the output clock itself. The first method for measuring jitter is commonly referred to as absolutely jitter or long-term jitter; use the second method to measure jitter called tracking jitter or input-output jitter (this time the other signal means a .reference signals), if the reference signals is cyclical (and therefore no jitter), the output signal of absolutely jitter and tracking jitter are equivalent; the use of the third approach measurements of jitter (relative to the output clock) often referred to as periodic .(or cycle-cycle) jitter. In a single clock cycle (or at several clock cycle), cycle-cycle jitter can be as time transform deviation measurements (called the cycle-cycle jitter nth). <br> You can use RMS output .jitter (RMS), also available peak-peak value. RMS jitter only those with a small amount of RMS with far more than the larger than the size of the edge of time displacement to indicate when the deterioration of smaller applications of worthwhile. .Such applications can include video and audio signals. Peak-peak jitter only for those who cannot tolerate any time beyond some absolute displacement of the edge of the application. Peak-peak jitter specifications in General is the only one that can be used to synchronize digital .system jitter specifications, this is because most of the establishment or maintenance time fault on chip operations are disastrous. <br> Given the importance of jitter measurement method also depends on the application of PLL. In General, the cycle-cycle jitter PLL in all .applications are important. Track the jitter in the PLL output clock is used to enter another clock domain or a domain by another clock output of the data-driven or sampling applications (application interface is an example) is important. Long-term jitter in the .clock multiplier applications sometimes is important. <br> Because PLL phase error in multiple cycles continue to accumulate, resulting from the power supply and substrate noise PLL tracking jitter may cycle-cycle jitter number times. However, as power and substrate noise suppression performance often .poor chip clock distribution network will generate additional noise. Therefore, to design the excellent PLL, the visible differences likely less than 2 times. <br> PLL frequency doubling in cycle-cycle jitter is also available for each benchmark cycle first one or two output .cycle period of periodic disturbance and increase the disturbance is a phase detector system error. <br> Jitter measurement can be very complex. We know, PLL must have noise mixed signal environment. Therefore, the equivalent of noisy environment measurement it is very important. .In a quiet, low-noise measurement in the PLL is optimistic and misleading results of jitter. Similarly, when human noise is added to the power of analog PLL, must pay attention to capture the worst cases of noise frequency content. For long term jitter .and tracking jitter, the worst case noise signal is a located on or below the loop bandwidth frequency (it usually is the minimum of PLL frequency low 20 x) square. For cycle-cycle jitter, worst case noise signal is an edge transition time is .less than the PLL output clock cycle and lower frequency than the base frequency of the square wave. The noise signal frequency bandwidth can be higher than the loop. <br> The appended with additional noise PLL for characteristics of the circuit board sets and optional chip .set. External pulse generator will low frequency noise coupled to a square wave is used for power supply noise test AVDD (analog PLL power) or coupled to AVDD and at the same time for substrate noise test AVSS (negative analog PLL power). The noise .(its level to control the base potential VSS) at the same time to AVDD and AVSS, and only the noise to the substrates are equivalent. As long as you can reach the PLL power, you can pass a Board (including the production of printed .circuit board) for processing to enhance these features. <br> Noise characteristics of processing <br> Only surface mount components should be used for power supply noise coupling network. The Jitter measurement that prior to the conduct noise on the power characteristics. Although the .PLL is extra high frequency noise added to power, but the additional noise should be ignored, because it concerned with PLL output. <br> Cycle-cycle jitter can be triggered by the PLL output, and observe an oscilloscope cycle after a similar move to .the edge of the measurement period. Tracking jitter and long-term jitter can be triggered by the PLL reference input, and observe the oscilloscope first PLL output edges move to measurement period. When inputs and PLL output signals from the same external drive oscilloscope for tablets ., you can eliminate those unrelated to PLL clock output pathway interference jitter. <br> For both types of measurement should use the noise of relatively low baseline clock..